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HMNR328D(V)
5.0 or 3.3V, 256K bit (32 Kbit x 8) TIMEKEEPER NVSRAM Part No. HMNR328D(V)
GENERAL DESCRIPTION The HMNR328D(V) TIMEKEEPER SRAM is a 32Kb x 8 non-volatile static RAM and real time clock organized as 32,768 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock solu tion. The HMNR328D(V) directly replaces industry standard 32Kbit x 8 SRAMs. It also provides the non-volatility of Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. FEATURES INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and CRYSTAL BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES : (VPFD = Power-fail Deselect Voltage) - HMNR328D : VCC = 4.5 to 5.5V 4.2V VPFD 4.5V - HMNR328DV: VCC = 3.0 to 3.6V 2.7V VPFD 3.0V CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS 10 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION COMPATIBLE WITH INDUSTRY STANDARD 32K x 8 SRAMS SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE
OPTIONS
w Timing 70 ns 85 ns 100 ns
MARKING
-70 -85 -100
PIN ASSIGNMENT
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3
28-pin Encapsulated Package
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HMNR328D(V)
FUNCTIONAL DESCRIPTION
The HMNR328D(V) is a full function, year 2000 compliant (Y2KC), real - time clock/calendar (RTC) and 32k x 8 non-volatile static RAM. User access to all registers within the HMNR328D (V) is accomplished with a bytewide interface . The Realtime clock (RTC) information and control bits reside in the sixteen upper most RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 -hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The HMNR328D(V) also contains its own power-fail circuitry which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
BLOCK DIAGRAM
OSCILLATOR AND CLOCK CHAIN 32.768KHz CRYSTAL
16 x 8 TIMEKEEPER REGISTER
A0 ~ A14 POWER 32,752 x 8 SRAM ARRAY VPFD VOLTAGE SENSE AND SWITCHING CIRCURITY
LITHIUM CELL
DQ0 ~ DQ7
/CE /WE /OE
Vcc A0-A14 : Address Input /CE : Chip Enable Vss : Ground DQ0-DQ7 : Data In / Data Out
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Vss /WE : Write Enable /OE : Output Enable VCC : Power (+5V or +3.3V) NC : No Connection
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Absolute Maximum Ratings
Symbol TA TSTG TSLD
(1)
HMNR328D(V)
Parameter AmbientOperatingTemperature Storage Temperature(Vcc Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltage Supply Voltage Output Current Power Dissipation HMNR328D HMNR328DV
Value 0 to 70 -40 to 70 260 -0.3 to Vcc+0.3 4.5 to 5.5 3.0 to 3.6 20 1
Unit C C C V V V mA W
VIO VCC IO PD
Note : Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. (1) Soldering temperature not to exceed 260 C for 10 seconds (Total thermal budget not to exceed 15 0 C for longer than 30 seconds). Caution : Negative undershoots below - 0.3V are not allowed on any pin while in the Battery Back -up mode.
Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL ) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages HMNR328D 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 HMNR328DV 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pS nS V V
AC Measurement Load Circuit
Note : 50pF for HMNR328DV
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Capacitance
Symbol CIN COUT Note : 1. 2. 3.
(3)
HMNR328D(V)
Parameter
(1,2)
Min
Max 10 10
Unit pF pF
Input Capacitance Input/Output Capacitance
Effective capacitance measured with power supply at 5V ( HMNR328D) or 3.3V (HMNR328DV). Sampled only, not 100% tested. At 25 C, f = 1MHz. Outputs deselected.
DC Characteristics
Symbol ILI ILO
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Battery Current OSC ON Battery Current OSC OFF Input Low Voltage Input High Voltage Output Low Voltage
Test Condition 0V VIN VCC
(1)
HMNR328D Min Typ Max 1 1 8 15 5 3 575 100 -0.3 2.2 0.8 VCC +0.3 0.4 0.4 2.4 2.0 3.6 100 100 4.1 4.35 4.5 800
HMNR328DV Min Typ Max 1 1 4 10 3 2 575 800 100 -0.3 2.0 0.8 VCC +0.3 0.4 0.4 2.4 2.0 3.6 70 100 2.7 2.9 VPFD3.0
Unit uA uA mA mA mA nA nA V V V V V V mA uA V
0V VOUT VCC Outputs open /CE=VIH /CE=VCC-0.2
ICC ICC1 ICC2
IBAT VIL VIH
IOL=2.1mA IOL=10mA IOH=-1.0mA IOUT2=-1.0uA VOUT1 > VCC-0.3 VOUT2>VBAT-0.3
VOL VOH VOHB IOUT1 IOUT2 VPFD
Output Low Voltage (open drain) (4) Output High Voltage VOH Battery Back-up VOUT Current (Active) VOUT Current (Battery Back-up) Power-fail Deselect Voltage Battery Back-up Switchover Voltage Battery Voltage
VSO VBAT
3.0 3.0
100 mV 3.0
V V
Note: 1. Valid for Ambient Operating Temperature: TA =0 to 70 C or 40 to 85 ; C VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. Outputs deselected. URL : www.hbe.co.kr Rev. 0.0 (January, 2002) 4 HANBit Electronics Co.,Ltd.
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OPERATING MODES
HMNR328D(V)
The 28-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single package. The clock locations conta in the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The seven clock bytes (7FFFh -7FF9h) are not the actual clock counters, they are memory locations consisting of READ/WRITE memory cells within the static RAM array. The HMNR328D includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The HMNR328D(V) also has its own Power-Fail Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data and clock operation until valid power is restored.
Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VCC 4.5V to 5.5V or 3.0V to 3.6V VSO to VPFD (min) VSO (1) /CE VIH VIL VIL VIL X X /OE X X VIL VIH X X /WE X VIL VIH VIH X X DQ7 - DQ0 High-Z DIN DOUT High High High Power Standby Active Active Active CMOS Standby Battery Backup
Note : X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
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READ Mode
HMNR328D(V)
The HMNR328D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE (Chip Enable) is low. The unique address specified by the 1 5 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable, providing the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be available after the latter of the Chip Enable Access Times ( tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while /CE and /OE remain active, output data will remain valid for Output Data Hold Time (tAXQX) but will go indeterminate until the next Address Access.
READ Mode AC Waveforms
/CE
/OE
Note : /WE = High.
READ Mode AC Characteristics
HMNR328D Symbol Parameter Min tAVAV tAVQV tELQV tGLQV
(2) tELQX
HMNR328D -100 Min 100 Max 100 100 50 10 5
HMNR328DV -85 Min 85 85 85 35 5 0 Max
Unit
-70 Max 70 70 35 5 5 25 25 10 10 70
READ Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
nS nS nS nS nS nS 25 25 nS nS nS
tGLQX tEHQZ
(2) (2) (2)
40 40 10
tGHQZ
tAXQX
Note: 1.Valid for Ambient Operating Temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF.
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WRITE Mode
HMNR328D(V)
The HMNR328D(V) is in the WRITE Mode whenever /WE (WRITE Enable) and /CE (Chip Enable) are low state after the address inputs are stable. The start of a WRITE is referenced from the latter occurring falling edge of /WE or /CE. A WRITE is terminated by the earlier rising edge of /WE or /CE. The addresses must be held valid throughout the cycle. /CE or /WE must return high for a minimum of tEHAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. /OE should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on /CE and /OE a low on /WE will disable the outputs tWLQZ after /WE falls.
WRITE AC Waveforms, WRITE Enable Controlled
A0-A14
WRITE AC Waveforms, Chip Enable Controlled
A0-A14
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WRITE Mode AC Characteristics
HMNR328D Symbol Parameter
(1)
HMNR328D(V)
HMNR328D -100 Min 100 0 0 80 80 10 10 50 50 5 5 Max
HMNR328DV -85 Min 85 0 0 55 60 0 0 30 30 0 0 Max nS nS nS nS nS nS nS nS nS nS nS 25 65 65 5 nS nS nS nS Unit
-70 Min Max 70 0 0 50 55 0 0 30 30 5 5 25 60 60 5 80 80 5
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ
(2,3)
WRITE Cycle Time Address Valid to WRITE Enable Low Address Valid to Chip Enable Low WRITE Enable Pulse Width Chip Enable Low to Chip Enable High WRITE Enable High to Address Transition Chip Enable High to Address Transition Input Valid to WRITE Enable High Input Valid to Chip Enable High WRITE Enable High to Input Transition Chip Enable High to Input Transition WRITE Enable Low to Output High-Z Address Valid to WRITE Enable High Address Valid to Chip Enable High WRITE Enable High to Output Transition
50
tAVWH tAVEH tWHQX
(2,3)
Note : 1. Valid for Ambient Operating Temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If /CE goes low simultaneously with /WE going low, the outputs remain in the high impedance state.
Data Retention Mode
With valid VCC applied, the HMNR328D(V) operates as a conventional Bytewide static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as " Don't care." Note : A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The HMNR328D(V) may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data and powering the clock. The internal energy source will maintain data in the HMNR328D(V) for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC . Write protection continues until VCC reaches VPFD (min) plus tREC (min). Normal RAM operation can resume tREC after VCC exceeds VPFD (max).
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Power Down/Up Mode AC Waveforms
HMNR328D(V)
Power Down/Up AC Characteristics
Symbol tF
(2)
Parameter VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSS VCC Fall Time HMNR328D HMNR328DV
Min 300 10 150 10 40 5
Max
Unit uS uS uS uS
tFB
(3)
tR
(4) tREC
VPFD (min) to VPFD (max) VCC Rise Time VPFD (max) to RST High VSS to VPFD (min) VCC Rise Time
200
uS uS
tRB Note :
1. Valid for Ambient Operating Temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 after s VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Power Down/Up Trip Points DC Characteristics
Symbol VPFD Parameter Power-fail Deselect Voltage
(1,2)
Min HMNR328D HMNR328DV 4.2 2.7
Typ 4.35 2.9 3.0 VPFD-100mV
Max 4.5 3.0
Unit V V V V YEARS
VSO TDR
(3)
Battery Back-up Switchover Voltage
HMNR328D HMNR328DV 10
Expected Data Retention Time
Note: 1. All voltages referenced to VSS . 2. Valid for Ambient Operating Temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 3. At 25 C.
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Register Map
Address 7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8 7FF7 7FF6 7FF5 7FF4 7FF3 7FF2 7FF1 7FF0 Keys : R = READ Bit W = WRITE Bit ST = Stop Bit 0 = Must be set to ' 0' BL = Battery Low Flag S = Sign Bit 0 0 0 0 0 0 ST W 0 0 0 0 0 0 R 0 0 0 0 0 0 0 Data D7 D6 0 0 FT 0 D5 0 0 10 Minutes 10 Seconds S 0 0 0 0 0 0 0 0 0 0 0 0 0 BL 0 0 0 0 0 0 0 D4 10M 0 0 D3 D2 Year Month Date : Day of Month Day Hours(24 Hour Format) Minutes Seconds Calibration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 Date 10 Hours D1 D0
HMNR328D(V)
Funtion / Range BCD Format Year Month Date Day Hours Minutes Seconds Control 00-99 01-12 01-31 01-07 00-23 00-59 00-59
10Years
1000 Years
100 Years 0
Century Flag
00-99
CLOCK OPERATIONS
The HMNR328D(V) offers 16 internal registers which contain TIMEKEEPER, and Control data. These registers are memory locations which contain external (user accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER Registers store data in BCD. Control Registers store data in Binary Format.
Reading the Clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a ' is written to the READ Bit, D6 in the 1' Control Register (7FF8h). As long as a ' remains in that position, updating is halted. After a halt is issued, the registers 1' reflect the count; that is, the day, date, and time that were current at the moment the halt command was is -sued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating occurs approximately 1 second after the READ Bit is reset to a ' 0.' URL : www.hbe.co.kr Rev. 0.0 (January, 2002) 10 HANBit Electronics Co.,Ltd.
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Setting the Clock
HMNR328D(V)
Bit D7 of the Control Register (7FF8h) is the WRITE Bit. Setting the WRITE Bit to a ' like the READ Bit, halts updates to 1,' the TIMEKEEPER reg-isters. The user can then load them with the correct day, date, and time data in 24-hour BCD format. Resetting the WRITE Bit to a ' then transfers the 0' values of all time registers (7FFh -7FF9h, 7FF1h) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE Bit is reset, the next clock update will occur approximately one second later. Note: Upon power-up following a power failure, both the WRITE Bit and the READ Bit will be reset to ' 0.'
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit is located at Bit D7 within the Seconds Register (7FF9h). Setting it to a ' stops the oscillator. When reset to a ' the HMNR328D oscillator starts within one 1' 0,' second. Note : It is not necessary to set the WRITE Bit when setting or resetting the STOP Bit (ST).
Calibrating the Clock
The HMNR328D(V) is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are factory calibrated at 25 C and tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 C, which equates to about 1.53 minutes per month. When the Calibration circuit is properly employed, accuracy improves to better than +1/-2 ppm at 25 C. The oscillation rate of crystals changes with temperature. The HMNR328D design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration bits occupy the five lower order bits (D4-D0) in the Control Register 7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120 actual oscillator cycles; that is, +4.068 or 2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. One method for ascertaining how much calibration a given HMNR328D(V) may require involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a nonuser serviceable enclosure. The designer could provide a simple utility that accesses the Calibration bits.
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Battery Low Warning
HMNR328D(V)
The HMNR328D(V) automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 7FF0h, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24hour interval. If a battery low is generated during a power -up sequence, this indicates that the battery is below approximately 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during
Power Supply Decoupling and Undershoot Protection
Note: ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 uF is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount).
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PACKAGE DIMENSION
Dimension A B C D E F G H I J Unit : inch Min 1.470 0.710 0.365 0.012 0.008 0.590 0.017 0.090 0.075 0.120 Max 1.500 0.740 0.375 0.013 0.630 0.023 0.110 0.110 0.150
HMNR328D(V)
J A H G
I B C D E F
ORDERING INFORMATION
H M N R 32 8 D V - 70 I
Operating Temperature : I = Industrial Temp. (-40~85 C ) Blank = Commercial Temp. (0~70C)
Speed options : 70 = 70 ns 85 = 85 ns 100 = 100ns Operating Voltage Dip type package Device : 32K x 8 Nonvolatile Timekeeping SRAM HANBit Memory Module
: Blank = 5V
V = 3.3V
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